1. Field of Invention
This invention relates to a method and apparatus for testing semiconductor devices, and more specifically, to a method and apparatus for applying pre-existing test patterns to a single integrated circuit incorporating two or more pre-existing logic blocks (cores) for which the test patterns already exist.
2. Description of the Related Art
Testing integrated circuits is a key component of the manufacturing process. In many designs, existing module cores, i.e., blocks of logic that have been previously designed, are reused in different applications. For instance, a processor (e.g. a '386) may exist as a core block of logic which can be integrated into any of a number of different applications on different integrated circuits. Integrating two or more pre-existing cores into an integrated circuit for a new application can lead to unique testing problems.
The time to market requirements for such a product make it extremely difficult to develop a complete set of test vectors from scratch in a timely manner. Additionally, many of the existing logic cores were not designed originally with an emphasis on design for testability techniques. Thus, it is difficult to apply standard design for test (DFT) techniques without significantly modifying the core design to achieve the desired fault coverage for such chips. Such standard design for test techniques include level sensitive scan design (LSSD) and other scan approaches which allow access to internal registers, both to apply test patterns and to observe test results. Additionally, fault simulation on extremely large designs imposes severe time penalties, making it difficult to assure a high fault coverage for the integrated design. The costs are prohibitive in terms of time and manpower, to develop a completely new set of test vectors for logic cores which are being integrated and which do not have standard DFT techniques implemented.
For newly designed integrated circuits utilizing more than one existing core, there may be fewer input/output (I/O) pins available on the new integrated circuit than the combined I/O requirements of the existing cores. This makes the access to the cores to apply the previously developed test vectors difficult.
One potential solution to this problem is to incorporate scan registers to provide inputs for each I/O pin for the core which is not accessible from the pins of the new integrated circuit. These scan registers function as the source of the test pattern signal for inaccessible core I/O pins. Scan registers could also be used to store test results. The scan registers must be loaded for each vector applied and unloaded to get the test results. Such scan solutions are time consuming in conducting the testing and may require significant additional chip area to accommodate the scan registers.
FIG. 1a shows a typical core 10 for which test patterns are developed. FIG. 1b shows the test patterns 140 as a set of 1 to m test vectors 150 having a vector length of n for each vector. The core 10 has input pins shown generally as 120 and 121, output pins generally shown as 122 and bidirectional input/output (I/O) pins 123. In order to test the core 10, each of the test vectors from test set 150 are applied to the input pins and bidirectional pins during a particular clock cycle.
The application of each particular test vector pattern will result in the core under test 10 outputting results from the output pins (and certain of the bidirectional pins) according to the input pattern applied. These results are then compared to expected results in order to determine whether the core under test performed satisfactorily. This sequence of applying the test vector and comparing the test vector to expected results is continued until the entire set of m test vectors has been applied.
Where design for test techniques have not been incorporated into the cores, the test patterns typically are functional patterns developed to test the core. More advanced design for test techniques provide observation points for an applied test pattern internal to the integrated circuit under test, such that the results from the applied test pattern can be monitored at multiple internal input nodes and can be compared to expected results. However, scan architectures typically used in such advanced techniques cause the testing to be time consuming. The input/output lines, including the bidirectional lines, indicated in FIG. 1a include signal I/O, i.e., data and control lines. In addition to the signal I/O, the core under test will have the required power and ground lines.
When two or more existing cores such as core 10 are integrated into a device, it is time consuming to develop a whole new set of test vectors to test the new device.
If test vectors, which were created to test cores in previous designs, can be used for a new design incorporating those cores, the test generation time for the new cores could be reduced, the need for extensive fault simulation for the new design would be eliminated and high quality tests could be maintained. Development of a full set of test vectors in a short period of time while integrating two or more cores into a single integrated circuit is desirable.